`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:02:30 10/24/2012 
// Design Name: 
// Module Name:    SCALE_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SCALE_UNIT #(parameter WIDTH_IN=16, WIDTH_OUT=16, MSB=16)
(

	 input clk,
	 input rst,
	 input signed[WIDTH_IN-1:0] data_in,
	 output reg signed[WIDTH_OUT-1:0] data_out

    );
	 
	always@(posedge clk or negedge rst)
	if(!rst)
		data_out[WIDTH_OUT-1:0] <= 0;
	else
	begin
		data_out[WIDTH_OUT-1:WIDTH_OUT-1] <= data_in[WIDTH_IN-1:WIDTH_IN-1];
		data_out[WIDTH_OUT-2:0] <= data_in[MSB-1-1:MSB-WIDTH_OUT];
	end

endmodule
